Electronic assembly

ABSTRACT

An electronic system having a sandwich design and including two carriers, each carrier having a printed circuit layer, the upper printed circuit layer being positioned on different planes.

BACKGROUND INFORMATION

A power module is known from PCT International Patent Publication No. WO98/15005, in which power transistors are mounted between two DBC (directbonded copper) substrates having structured CU layers as the wiringlevel, the fronts and backs of the chips being bonded to the CU layersvia a solder layer. If necessary, optional spacer balls may be used toensure that the solder layer on the structured metal layers on the frontof the chips retains an adequate thickness during and after the reflowsoldering process. One feature of the DBC substrate is that the CUlayers cannot be structured to just any fineness, due to theirthickness—typically approximately 300 μm. The CU layer's thickness isnecessary to adequately dissipate heat loss from the power chips and toconduct the high currents in the module with as little resistance aspossible. As a result, the minimum distance between two CU areas cannotbe much smaller than the thickness of the CU layer.

SUMMARY OF THE INVENTION

A major disadvantage of the design known from the related art is that itis suitable only for mounting preferably roughly structured front leadsof power chips and uniform chip thicknesses. As a result, it is notpossible to combine power components (power chips) and signal components(signal ICs) if the signal ICs have a large number of finely structuredfront leads, and if the signal ICs have chip thicknesses that deviatesubstantially from the power chip thicknesses. The electronic systemaccording to the present invention has the advantage over the relatedart that it enhances the module design very easily and economically bycombining power chips and signal ICs.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows a first exemplary embodiment of the electronic system.

FIG. 2 shows a second exemplary embodiment of the electronic system.

FIG. 3 shows an upper DBC substrate prior to punching and embossing.

FIG. 4 shows an upper DBC substrate after punching and embossing.

DETAILED DESCRIPTION

FIG. 1 shows a module design of an electronic system according to thepresent invention for a first embodiment of the present invention. Theelectronic system includes a first carrier 10 and a second carrier 11. Aplurality of electronic circuits in the form of semiconductor chips,which are identified in FIG. 1 by reference numbers 21, 22 and 23, areordinarily positioned between carriers 10, 11. According to the presentinvention, it is possible to provide fewer than three semiconductorchips 21, 22, 23 between carriers 10, 11 as well as a larger number ofsuch semiconductor chips 21, 22, 23. In FIG. 1, a first and a secondpower semiconductor chip are identified by reference numbers 21 and 22.Power semiconductor chips 21, 22 are characterized by the fact that, inparticular, a great amount of heat, which is dissipated, if necessary,within power semiconductor chips 21, 22, must be discharged via thermalcouplings. Therefore, reference number 23 in FIG. 1 identifies a signalIC that is provided for signal processing. Signal IC 23 ordinarily hasmuch lower heat dissipation requirements than power semiconductor chips21, 22. In the case of signal IC 23 according to FIG. 1, thesemiconductor substrate of signal IC 23 is thicker than thesemiconductor substrate of the two power semiconductor chips 21, 22.

FIG. 2 also shows the electronic system according to the presentinvention, first carrier 10, second carrier 11 and semiconductor chips21, 22, 23 again being provided. In contrast to FIG. 1, however, thethickness of signal IC 23 in FIG. 2 is smaller than the thickness ofpower semiconductor chips 21, 22.

Both FIG. 1 and FIG. 2 are described together below, however including adiscussion of the differences. An essence of the present invention isthe use of a special second carrier 11 in such a way that sub-areas ofsecond carrier 11 have a finely structured contact layer that isadjustable in distance relative to lower first carrier 10, allowingsignal IC chips to be cost-effectively integrated into the overallmodule or into the complete electronic system without changing themodule assembly procedure over that of the related art.

First carrier 10, which is also referred to below as lower carrier 10,includes, in particular, a ceramic material as the carrier substance towhich a lower contact layer 8 is applied in sub-areas—i.e., lowercontact layer 8 is structured. Lower contact layer 8 is providedaccording to the present invention, in particular, as a copper layer,which is also referred to below as lower CU layer 8. Lower carrier 10,along with lower contact layer 8 located thereon, is provided accordingto the present invention, in particular, as a DBC substrate and istherefore also referred to below as lower DBC substrate 10. In both FIG.1 and FIG. 2, an electrically and thermally conductive connection onlower CU layer 8 of lower carrier 8 is provided individually to each ofsemiconductor chips 21, 22, 23 in the form of lower solder layers 7.

Semiconductor chips 21, 22, 23 also have leads on their fronts and backswhich are supplied by the second carrier, i.e., upper carrier 11. Uppercarrier 11 is provided according to the present invention, inparticular, also as a DBC substrate and is therefore also referred to asupper DBC substrate 11. Upper carrier 11 has recesses 12 in sub-areas. Acontact layer that is identified by reference number 13 in the areaswhere the upper carrier does not have a recess 12 and is identified byreference number 14 in the areas where upper carrier 11 does have recess12, is also provided on upper carrier 11. Upper contact layer 13, 14,which is provided according to the present invention, in particular,also as CU layer 13, 14, is used to contact the top of semiconductorchips 21, 22, 23. Because the contact layer does not come into contactwith upper carrier 11 in its areas 14, it is possible for “free contactlayer” 14 to have a limited flexibility in a direction positioned atright angles to the plane of upper carrier 11. As a result, free contactlayer 14 is bendable, i.e., plastically deformable, in the upwarddirection, i.e., in the direction of second carrier 11, so that uppercontact layer 13, 14 as a whole is able to contact a thinner powersemiconductor chip 21, 22 and also electrically contact a thicker signalIC 23, even though the power semiconductor chip and the signal IC chipare positioned at the same level from the perspective of their lowersides, i.e., from first carrier 10, contact layer 8 and solder layer 7.FIG. 2 shows the opposite case, namely one in which signal IC chip 23 isthinner than power semiconductor chips 21, 22. In this second embodimentof the electronic system according to the present invention, free area14 of upper contact layer 13, 14 is therefore plastically deformed in adownward direction, so that, once again, it is ensured that uppercontact layer 13, 14 as a whole contacts power semiconductor chips 21,22 and signal IC chip 23. According to the present invention, therefore,upper contact layer 13, 14 is located on a first plane in its area 13that does not have a recess 12, while it is at least partiallypositioned on a second plane that differs from the first plane in its“free” area 14.

According to the present invention, both embodiments are designed sothat a solder layer 15, which has spacer balls which are not identifiedin greater detail by a reference number, is provided between uppercontact layer 13, 14 and the semiconductor chips.

FIG. 3 shows upper carrier 11 and upper contact layer 13. In the centralarea of upper carrier 11, recess 12 is represented by a dottedrectangle. FIG. 3 also shows areas 13 of upper contact layer 13, 14,which are provided in areas of upper carrier 11 where recess 12 is notprovided. Areas 14 of upper contact layer 13, 14 which are provided inthe area of recess 12 are also shown. According to the presentinvention, free areas 14 of upper contact layer 13, 14 are provided withadditional structuring in the area of recess 12 (for example, using astamping die) that is finer than the structuring of upper contact layers13, 14 provided in the area of upper carrier 11 at locations whererecess 12 is not present.

FIG. 4 shows an additional and finer structuring of this type, whereupper carrier 11 is illustrated with structuring layer 13, 14 and recess12, the difference between FIG. 4 and FIG. 3 being that free areas 14 ofupper contact layer 13, 14 are more finely structured. Based on theunstructured central area of free upper contact layer 14 identified byreference letter M and shown in FIG. 3, free area 14 of upper contactlayer 13, 14 is finely structured, in particular in the form of finelystructured leads which are designed, in particular, for signal IC chips23.

The structuring step marking the transition from FIG. 3 to FIG. 4 isprovided according to the present invention, in particular, as apunching and embossing process. However, other mechanical and/or otherstructuring methods are also provided according to the presentinvention. In the case of the punching and embossing process accordingto the present invention, free areas 14 of the upper contact layer aregeometrically structured, i.e., structuring along the plane of uppercarrier 11, as well as structuring in the orthogonal direction thereto,i.e., excursions of free areas 14 of upper contact layer 13, 14 areprovided to compensate for different thicknesses of the semiconductorchips provided in the region of free areas 14 of the upper contactlayer.

According to the present invention, this makes it advantageouslypossible to provide chips 21, 22, 23 of different thicknesses in asingle, sandwich-type electronic system according to the presentinvention. It is therefore also advantageously possible, according tothe present invention, to integrate signal ICs having finely structuredleads and having a large number of leads into the electronic systemaccording to the present invention that is designed, in particular, as apower module. Advantageously, according to the present invention, noadditional parts are needed. Another advantage of this, according to thepresent invention, is that an unmodified module assembly procedure maybe used, i.e., it is possible to assemble all chips in a reflowsoldering process. The electronic system according to the presentinvention is also economical because the minimal additional cost forpunching and embossing the as yet componentless DBC substrate in a dieis made possible by multiple substrate utilization. The term multiplesubstrate utilization means combining multiple individual substrates forsimultaneous processing. According to the present invention, it isfurther possible to use the fine structuring of free areas 14 of uppercontact layer 13, 14 in the area of the external leads of the electronicsystem according to the present invention to substantially increase thenumber of external leads of the module. Another advantage is that,according to the present invention, both signal ICs 23 and power chips21, 22 are mountable on the same plane on lower carrier 10, or on itscontact layer 8. This makes it possible to continue mounting thecomplete power module or the complete electronic system over the entirefront and back, i.e., in a thermally optimum manner.

According to the related art, the signal ICs are mounted on the externalsurface of the module, thereby preventing extensive cooling on bothsides of the module.

According to the present invention, upper carrier 11 of the electronicsystem according to the present invention and its contact layer 13, 14have the following properties: In the area of power chips 21, 22, thedesign of DBC layer 11 remains the same vis-à-vis an upper carrier 11without recess 12.

In the areas in which signal ICs 23 are to be connected with the help offree areas 14 of upper contact layer 13, 14, the ceramic area of thesubstrate, i.e., upper carrier 11, has a recess—i.e., recess 12 orrecesses 12 are provided—and contact layer 13, 14, which was originallytypically 300 μm thick, is modified by a punching and embossingoperation so that a finely structured contacting of signal IC 23, whichis adjusted in height, i.e., in the orthogonal direction relative to theplane of upper carrier 11, to the thickness of signal IC 23 may beprovided without having to modify the assembly procedure for the entiremodule or the entire electronic system. Contact layer 13, 14 may beadjusted to both thicker and thinner IC chips 23 in its free area 14,compared to power chips 21, 22. To punch and emboss the upper contactlayer as easily as possible in the IC contact area of recess 12, it maybe optionally helpful, according to the present invention, to provideupper contact layer 13, 14 with a thinner design in the embossing area,i.e., in free area 14, prior to sintering it onto upper carrier 11,i.e., for example using a thickness of approximately 50 μm to 250 μm.

1-5. (canceled)
 6. A sandwich-type electronic system comprising: a firstcarrier; and a second carrier situated substantially parallel to thefirst carrier, wherein the first carrier has a first printed circuitlayer on a side facing the second carrier, wherein the second carrierhas a second printed circuit layer on a side facing the first carrier,and wherein the second printed circuit layer is situated partially on afirst plane, and the second printed circuit layer, in a sub-area, issituated at least partially on a second plane.
 7. The electronic systemaccording to claim 6, wherein the second carrier has a recess in thesub-area.
 8. The electronic system according to claim 6, furthercomprising at least one signal IC situated in the sub-area between thefirst and second carriers.
 9. The electronic system according to claim8, further comprising at least one power semiconductor chip situatedbetween the first and second carriers outside the sub-area.
 10. Theelectronic system according to claim 9, wherein the signal IC and thepower semiconductor chip have different thicknesses.